As electronic devices or electronic parts, those in each of which a semiconductor element called a chip is mounted on a substrate are generally used. A flip-chip method (FC method) is one of methods for mounting an element on a substrate. In the flip-chip method, a silicon chip and a metal electrode pad are connected to each other by a projecting terminal which is made of a metal composition and called a bump. When the silicon chip and the metal electrode pad are connected to each other by a bump, an alloy layer is generated in a connection interface each of between the bump and the chip and between the bump and the substrate, and electrical bonding may be caused. The flip-chip method is widely used since it is advantageous in that a mounting area is small, a gap between an element and a substrate is narrow, and electrical properties are favorable.
As more electronic parts are mounted by the flip-chip method, various sizes of chips or substrates are desired. For example, there is a problem in that conduction reliability in bonding deteriorates for the following reason.
In general, chips and substrates have different thermal expansion coefficients depending on the different materials or thicknesses. For this reason, after a substrate which is bonded to a chip by a bump is mounted in an electronic device, the chip and the substrate may be heated by heat inside the electronic device. When the electronic device is heated, the chip and the substrate warp, and a gap between the chip and the substrate becomes large. When the gap between the chip and the substrate becomes large, there is a problem that bonding between the chip and the substrate breaks and conduction is not obtained. This easily becomes prominent when the sizes of the chip and the substrate are large.
In addition, when the chip and the substrate are small, the size of the bump is decreased. Therefore, there is a problem that a contact area between the bump and the chip or substrate is decreased and it is difficult to obtain conduction.
In order to resolve this problem, a method for setting the bump to have a layered structure is used. However, in setting the bump to have a layered structure, it is desired to apply an energy for forming an alloy layer on the same location of the chip a plurality of times, so that there is a problem that destruction of the chip is caused as illustrated in FIG. 1B. In addition, when an energy for forming a bump is small, there is a problem that the bump is not bonded as illustrated in FIG. 1A. In this regard, in the suggestion, deterioration of conduction reliability in bonding due to warping of the substrate or miniaturization of the bump is not avoided.
Deterioration of conduction reliability in bonding between the chip and the substrate is also caused by a phenomenon in which a metal contained in the bump is diffused inside the alloy layer, erodes the alloy layer, and voids (hollows) are generated inside the alloy layer. When the voids are generated, a value of resistance of the alloy layer is increased and conduction reliability in bonding deteriorates.
In recent years, cases where electronic devices or electronic parts are used have been further increased, and also higher performance of the electronic parts has been desired. With this, materials used in substrates are changed. As the materials, materials (for example, SiC, GaN, and the like) that may increase outputs compared to silicon which has been used may be used. Along with these materials, materials of chips which are connected to bumps are also changed. For example, generation of voids becomes prominent when a bump containing gold is formed into a chip containing aluminum. Therefore, the current situation is that, with the present bump, it is difficult to maintain conduction reliability in bonding.
The followings are reference documents.    [Document 1] Japanese Laid-open Patent Publication No. 2001-257229 and    [Document 2] Japanese Laid-open Patent Publication No. 2000-164619.